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1 ltc1067/ltc1067-50 rail-to-rail, very low noise universal dual filter building block features descriptio n u the ltc ? 1067/ltc1067-50 consist of two identical rail- to-rail, high accuracy and very wide dynamic range 2nd order switched-capacitor building blocks. each building block, together with three to five resistors, provides 2nd order filter functions such as bandpass, highpass, lowpass, notch and allpass. high precision 4th order filters are easily designed. the center frequency of each 2nd order section is tuned by the external clock frequency. the internal clock-to-center frequency ratio (100:1 for the ltc1067 and 50:1 for the ltc1067-50) can be modified by the external resistors. these devices have a double sampled architecture which places aliasing and imaging components at twice the clock frequency. the ltc1067-50 is a low power device con- suming about one half the current of the ltc1067. the ltc1067-50s typical supply current is about 1ma from a 3.3v supply. the ltc1067 and ltc1067-50 are available in 16-pin narrow ssop and so packages. mask programmable versions of the ltc1067 and ltc1067-50, with thin film resistors on-chip and custom clock-to-cutoff frequency ratios, can be designed in an so-8 package to realize application specific monolithic filters. please contact ltc marketing for more details. , ltc and lt are registered trademarks of linear technology corporation. typical applicatio n u frequency response frequency (khz) 8 gain (db) 12 1067 ?ta02 9 10 11 0 ?0 ?0 ?0 ?0 0.1 m f 1067 ta01 ltc1067-50 v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b 3.3v r32, 200k r22, 10k r31, 200k r21, 10k r11 200k in rb1, 200k out 1 m f f clk = 500khz total output noise: 90 v rms s/n ratio: 80db 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n rail-to-rail input and output operation n operates from a single 3v to 5v supply n dual 2nd order filter in a 16-lead ssop package n > 80db dynamic range on single 3.3v supply n clock-to-center frequency ratio of 100:1 for the ltc1067 and 50:1 for the ltc1067-50 n internal sampling-to-center frequency ratio of 200:1 for the ltc1067 and 100:1 for the ltc1067-50 n center frequency error < 0.2% typ n low noise: < 40 m v rms , q 5 n customizable with internal resistors applicatio n s u n notch filters n narrowband bandpass filters n tone detection n noise reduction systems single 3.3v supply rail-to-rail, 4th order, 10khz bandpass filter
2 ltc1067/ltc1067-50 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u order part number total voltage supply (v + to v C ) .............................. 12v input voltage ........................ (v + + 0.3v) to (v C C 0.3v) output short-circuit duration .......................... indefinite power dissipation ............................................... 500mv operating temperature range ltc1067c ............................................... 0 c to 70 c ltc1067i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c consult factory for military grade parts. ltc1067 (internal op amps) v s = 4.75v, t a = 25 c, unless otherwise noted. parameter conditions min typ max units operating supply range 311v positive output voltage swing v s = 3v, r l = 10k l 2.65 2.80 v v s = 4.75v, r l = 10k l 4.25 4.50 v v s = 5v, r l = 10k l 4.15 4.50 v negative output voltage swing v s = 3v, r l = 10k l 0.020 0.200 v v s = 4.75v, r l = 10k l 0.025 0.225 v v s = 5v, r l = 10k l C 4.96 C 4.80 v output short-circuit current v s = 3v 16/1.0 ma (source/sink) v s = 4.75v 33/2.2 ma v s = 5v 70/7.2 ma dc open-loop gain r l = 10k 90 db gbw product r l = 10k 2.8 mhz slew rate r l = 10k 2.25 v/ m s ltc1067 (complete filter) v s = 4.75v, f clk = 250khz, t a = 25 c, unless otherwise noted. electrical characteristics parameter conditions min typ max units center frequency range, f o (note 1) 0.001 to 20 khz input frequency range 0 to 1 mhz clock-to-center frequency, f clk /f o v s = 3v, f clk = 250khz, mode 1, f o = 2.5khz, q = 5 100:1 0.2 % r1 = r3 = 49.9k, r2 = 10k l 0.70 % v s = 4.75v, f clk = 250khz, mode 1, f o = 2.5khz, q = 5 100:1 0.2 % r1 = r3 = 49.9k, r2 = 10k l 0.70 % v s = 5v, f clk = 500khz, mode 1, f o = 5khz, q = 5 100:1 0.2 % r1 = r3 = 49.9k, r2 = 10k l 0.70 % clock-to-center frequency ratio, v s = 3v, f clk = 250khz, q = 5 l 0.1 0.35 % side-to-side matching v s = 4.75v, f clk = 250khz, q = 5 l 0.1 0.35 % v s = 5v, f clk = 500khz, q = 5 l 0.1 0.35 % top view s package 16-lead plastic so gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b t jmax = 110 c, q ja = 135 c/ w (gn) t jmax = 110 c, q ja = 115 c/ w (s) ltc1067cgn ltc1067-50cgn ltc1067ign ltc1067-50ign ltc1067cs ltc1067-50cs ltc1067is ltc1067-50is
3 ltc1067/ltc1067-50 electrical characteristics parameter conditions min typ max units q accuracy v s = 3v, f clk = 250khz, q = 5 l 0.5 2% v s = 4.75v, f clk = 250khz, q = 5 l 0.5 2% v s = 5v, f clk = 500khz, q = 5 l 0.5 2% f o temperature coefficient 1 ppm/ c q temperature coefficient 5 ppm/ c dc offset voltage (see table 2) v os1 (dc offset of input inverter) l 3 18 mv v os2 (dc offset of first integrator) l 4 22 mv v os3 (dc offset of second integrator) l 4 22 mv clock feedthrough 150 m v rms maximum clock frequency q < 2.5, v s = 5v 2.0 mhz power supply current v s = 3v, f clk = 250khz l 2.50 4.5 ma v s = 4.75v, f clk = 250khz l 3.00 5.5 ma v s = 5v, f clk = 500khz l 4.35 7.5 ma ltc1067 (complete filter) v s = 4.75v, f clk = 250khz, t a = 25 c, unless otherwise noted. parameter conditions min typ max units center frequency range, f o (note 1) 0.001 to 40 khz input frequency range 0 to 1 mhz clock-to-center frequency, f clk /f o v s = 3v, f clk = 125khz, mode 1, f o = 2.5khz, q = 5 50:1 0.2 % r1 = r3 = 49.9k, r2 = 10k l 0.75 % v s = 4.75v, f clk = 125khz, mode 1, f o = 2.5khz, q = 5 50:1 0.2 % r1 = r3 = 49.9k, r2 = 10k l 0.75 % v s = 5v, f clk = 250khz, mode 1, f o = 5khz, q = 5 50:1 0.3 % r1 = r3 = 49.9k, r2 = 10k l 0.75 % clock-to-center frequency ratio, v s = 3v, f clk = 125khz, q = 5 l 0.2 0.55 % side-to-side matching v s = 4.75v, f clk = 125khz, q = 5 l 0.2 0.55 % v s = 5v, f clk = 250khz, q = 5 l 0.2 0.55 % q accuracy v s = 3v, f clk = 125khz, q = 5 l 0.5 2% v s = 4.75v, f clk = 125khz, q = 5 l 0.5 2% v s = 5v, f clk = 250khz, q = 5 l 0.5 2% ltc1067-50 (internal op amps) v s = 4.75v, t a = 25 c, unless otherwise noted. parameter conditions min typ max units operating supply range 2.7 11 v positive output voltage swing v s = 3v, r l = 10k l 2.65 2.80 v v s = 4.75v, r l = 10k l 4.25 4.50 v v s = 5v, r l = 10k l 4.15 4.50 v negative output voltage swing v s = 3v, r l = 10k l 0.020 0.200 v v s = 4.75v, r l = 10k l 0.025 0.225 v v s = 5v, r l = 10k l C 4.96 C 4.80 v output short-circuit current v s = 3v 16/0.6 ma (source/sink) v s = 4.75v 33/1.2 ma v s = 5v 70/5.7 ma dc open-loop gain r l = 10k 90 db gbw product r l = 10k 1.9 mhz slew rate r l = 10k 0.8 v/ m s ltc1067-50 (complete filter) v s = 4.75v, f clk = 125khz, t a = 25 c, unless otherwise noted.
4 ltc1067/ltc1067-50 electrical characteristics ltc1067-50 (complete filter) v s = 4.75v, f clk = 125khz, t a = 25 c, unless otherwise noted. parameter conditions min typ max units f o temperature coefficient 1 ppm/ c q temperature coefficient 5 ppm/ c dc offset voltage (see table 2) v os1 (dc offset of input inverter) l 3 18 mv v os2 (dc offset of first integrator) l 4 22 mv v os3 (dc offset of second integrator) l 4 22 mv clock feedthrough 150 m v rms maximum clock frequency q < 2.5, v s = 5v 2.0 mhz power supply current v s = 3v, f clk = 125khz l 1.00 2.5 ma v s = 4.75v, f clk = 125khz l 1.45 3.0 ma v s = 5v, f clk = 250khz l 2.35 4.0 ma the l denotes the specifications which apply over the full operating temperature range. note 1: see typical performance characteristics. ltc1067 maximum q vs center frequency (modes 2 where r4 < 10r2, 3) ltc1067 maximum q vs center frequency (modes 1, 1b, 2 where r4 3 10r2) center frequency, f o (khz) 0 maximum q 20 1067 g01 5 10 15 50 40 30 20 10 0 v s = 5v f clk(max) = 2mhz v s = 3.3v f clk(max) = 1mhz v s = 5v f clk(max) = 1.5mhz center frequency, f o (khz) 0 maximum q 20 1067 g02 5 10 15 50 40 30 20 10 0 v s = 3.3v f clk(max) = 1mhz v s = 5v f clk(max) = 1.5mhz v s = 5v f clk(max) = 2mhz input voltage (v rms ) 0.1 (noise + thd)/signal (db) 1 1067 g03 4th order butterworth lpf v s = single 3.3v, f in = 1khz f clk = 400khz, f ?db = 4khz r l = 20k mode 1 mode 3 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 2 ltc1067 noise + thd vs input voltage input voltage (v rms ) 0.1 (noise + thd)/signal (db) 1 1067 g04 4th order butterworth lpf v s = single 5v, f in = 1khz f clk = 500khz, f ?db = 5khz r l = 20k mode 1 mode 3 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 2 input voltage (v rms ) 0.1 1 5 1067 g05 (noise + thd)/signal (db) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 4th order butterworth lpf v s = 5v, f in = 1khz f clk = 500khz, f ?db = 5khz r l = 20k mode 1 mode 3 mode 2 ltc1067 noise + thd vs input voltage ltc1067 noise + thd vs input voltage typical perfor m a n ce characteristics u w input frequency (khz) 1345 (noise + thd)/signal (db) ?0 ?5 ?0 ?5 ?0 ?5 ?0 2 1067 g06 4th order butterworth lpf v s = single 3.3v f clk = 400khz, v in = 0.36v rms f ?db = 4khz, r l = 20k mode 1 mode 3 ltc1067 noise + thd vs input frequency
5 ltc1067/ltc1067-50 typical perfor m a n ce characteristics u w input frequency (khz) 1345 (noise + thd)/signal (db) ?5 ?0 ?5 ?0 2 1067 g07 4th order butterworth lpf v s = single 5v, f clk = 500khz v in = 0.5v rms, f ?db = 5khz, r l = 20k mode 1 mode 3 ltc1067 noise + thd vs input frequency input frequency (mhz) 13 10 1067 g08 245 6 78 9 (noise + thd)/signal (db) ?5 ?0 ?5 ?0 mode 1 mode 3 4th order lowpass butterworth v s = 5v, v in = 1v rms f clk = 1mhz, f ?db = 10khz r l = 20k q 0 noise ( v rms ) 220 200 180 160 140 120 100 80 60 40 20 0 40 1067 g09 10 20 30 50 5v 5v 3v ltc1067 noise vs q ltc1067 noise + thd vs input frequency ltc1067 output voltage swing vs load resistance, 5v supply voltage ltc1067 output voltage swing vs load resistance, single supply voltage load resistance (k to gnd) 10.0 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 output voltage swing (v p-p ) 1067 g10 10 0 2 4 6 8 12 14 16 18 20 v s = 5v load resistance (k to v ) output voltage swing (v p-p ) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1067 g11 10 0 2 4 6 8 12 14 16 18 20 v s = 5v v s = 3.3v ltc1067 power supply current vs power supply total power supply (v) 3 4.5 4.0 3.5 3.0 2.5 2.0 1.5 0 68 1067 g12 45 7910 power supply current (ma) 70 c 25 c ?0 c ltc1067-50 maximum q vs center frequency (modes 2 where r4 < 10r2, 3) ltc1067-50 maximum q vs center frequency (modes 1, 1b, 2 where r4 3 10r2) center frequency, f o (khz) 0 maximum q 40 1067 g13 10 20 30 50 40 30 20 10 0 v s = 3.3v f clk(max) = 800khz v s = 5v f clk(max) = 1.5mhz v s = 5v f clk(max) = 2mhz v s = 3v f clk(max) = 600khz center frequency, f o (khz) 0 maximum q 40 1067 g14 10 20 30 50 40 30 20 10 0 v s = 3.3v f clk(max) = 800khz v s = 5v f clk(max) = 1.5mhz v s = 5v f clk(max) = 2mhz v s = 3v f clk(max) = 600khz ltc1067-50 noise + thd vs input voltage input voltage (v rms ) 0.1 (noise + thd)/signal (db) 1 1067 g15 4th order butterworth lpf v s = single 3v, f in = 1khz f clk = 200khz, f ?db = 4khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 2 mode 1 mode 3
6 ltc1067/ltc1067-50 typical perfor m a n ce characteristics u w ltc1067-50 noise + thd vs input voltage ltc1067-50 noise + thd vs input frequency ltc1067-50 noise + thd vs input voltage input voltage (v rms ) 0.1 (noise + thd)/signal (db) 1 1067 g16 4th order butterworth lpf v s = single 5v, f in = 1khz f clk = 250khz, f ?db = 5khz r l = 20k ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 2 mode 1 mode 3 input voltage (v rms ) 0.1 1 5 1067 g17 (noise + thd)/signal (db) ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 4th order butterworth lpf v s = 5v, f in = 1khz f clk = 250khz (225khz for mode 2) f ?db = 10khz, r l = 20k mode 1 mode 2 mode 3 input frequency (khz) 1345 (noise + thd)/signal (db) ?0 ?5 ?0 ?5 ?0 ?5 ?0 2 1067 g18 4th order butterworth lpf v s = single 3v, f clk = 200khz v in = 0.34v rms, f ?db = 4khz, r l = 20k mode 1 mode 3 ltc1067-50 noise + thd vs input frequency ltc1067-50 noise vs q ltc1067-50 noise + thd vs input frequency input frequency (khz) 1345 (noise + thd)/signal (db) ?0 ?5 ?0 ?5 ?0 ?5 ?0 2 1067 g19 4th order butterworth lpf v s = single 5v, f clk = 250khz v in = 0.5v rms, f ?db = 5khz, r l = 20k mode 1 mode 3 input frequency (khz) 1345 (noise + thd)/signal (db) ?0 ?5 ?0 ?5 ?0 ?5 ?0 2 1067 g20 4th order butterworth lpf v s = 5v, f clk = 250khz v in = 1v rms , f ?db = 5khz r l = 20k mode 1 mode 3 q noise ( v rms ) 400 350 300 250 200 150 100 50 0 1067 g21 25 0 5 10 15 20 30 35 40 45 50 5v 5v 3v ltc1067-50 output voltage swing vs load resistance, 5v supply voltage load resistance (k to gnd) 10.0 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 output voltage swing (v p-p ) 1067 g22 10 0 2 4 6 8 12 14 16 18 20 v s = 5v ltc1067-50 output voltage swing vs load resistance, single supply voltage load resistance (k to v ) output voltage swing (v p-p ) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1067 g23 10 0 2 4 6 8 12 14 16 18 20 v s = 5v v s = 3v total power supply (v) 3 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 68 1067 g24 45 7910 power supply current (ma) 70 c 20 c 25 c ltc1067-50 power supply current vs power supply
7 ltc1067/ltc1067-50 pi n fu n ctio n s uuu v + , v C (pins 1, 3,14) : the v + (pins 1, 3) and the v C (pin 14) should each be bypassed with a 0.1 m f capacitor to an adequate analog ground. the filters power supplies should be isolated from other digital or high voltage analog supplies. a low noise linear supply is recommended. using a switching power supply will lower the signal-to- typical perfor m a n ce characteristics u w ltc1067/ltc1067-50 mode 1b noise increase vs r5/r6 ratio ltc1067/ltc1067-50 mode 3 noise increase vs r2/r4 ratio r2/r4 ratio 0.2 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.5 0.7 1067 g26 0.3 0.4 0.6 0.8 0.9 1.0 relative noise increase (reference noise when r2/r4 = 1) noise ratio of the filter. the supplys power-up slew rate should be less than 1v/ m s. when v + is applied before v C , and v C is allowed to go above ground, a diode should clamp v C to prevent latch-up. figures 1 and 2 show typical connec- tions for dual and single supply operation. 0.1 m f 1067 f01 200 w ltc1067 ltc1067-50 clock source 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 star system ground digital ground plane v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b v + v 0.1 m f figure 1. dual supply ground plane connections figure 2. single supply ground plane connections 0.1 m f 106 7 f02 200 w ltc1067 ltc1067-50 clock source 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 star system ground digital ground plane v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b v + 1 m f for mode 3, the sa and sb summing node pins are tied to the agnd pin r5/r6 ratio 0 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 1.5 2.5 1067 g25 0.5 1.0 2.0 3.0 3.5 relative noise increase (reference noise when r5/r6 = 0.02)
8 ltc1067/ltc1067-50 pi n fu n ctio n s uuu sa, sb (pins 4, 13): summing inputs. the summing pins connection, along with the other resistor connections, determine the circuit topology (mode) of each 2nd order section. these pins should never be left floating. lpa, bpa, hpa/na, hpb/nb, bpb, lpb (pins 5, 6, 7, 10, 11, 12): output pins. each 2nd order section of the ltc1067 has three outputs which typically source 33ma and sink 2ma. driving coaxial cable, capacitive loads or resistive loads less than 10k will degrade the total har- monic distortion performance of any filter design. refer to output loading in the applications information section for more details. when evaluating the distortion or noise performance of a filter, the output should be buffered with a wideband amplifier. inv a, inv b (pins 8, 9): inverting input. these pins are the high impedance inverting inputs of internal op amps. they are susceptible to stray capacitance coupling to low impedance nodes such as signal outputs and power supply lines. resistors that are connected from a signal output to the inverting input pin should be located as close to the inverting input as possible. agnd (pin 15): analog ground. the filter performance depends on the quality of the analog signal ground. for either dual or single supply operation, an analog ground plane surrounding the package is recommended. the analog ground plane should be connected to any digital ground at a single point. for dual supply operation pin 15 is connected to the analog ground plane. for single supply operation pin 15 should be bypassed to the analog ground plane with at least a 1 m f capacitor. an on-chip resistive voltage divider sets the bias at one-half of the supply. clk (pin 16): clock input. any cmos logic clock source with a square-wave output and a 50% duty cycle ( 10%) is an adequate clock source for the device. the power supply for the clock source should not be the filters power supply. the analog ground for the filter should be con- nected to the clocks ground at a single point only. table 1 shows the clocks low and high level threshold values for dual supply or single supply operation. logic low level signals must be greater than the negative supply voltage. with a 5v power supply, the clock levels may be either 5v or 0v to 5v. logic high level signals should be less than the positive supply voltage. however, when the positive supply voltage is either 3v or 3.3v, the clock signal can be as high as 5.5v. table 1. clock source high and low threshold levels power supply high level low level 5v 3 2.2v 0.50v single 5v 3 2.2v 0.50v single 3v, 3.3v 3 2v 0.40v sine waves are not recommended for the clock input. the clock signal should be routed from the right side of the ic package to avoid coupling to any power supply lines or input or output signal paths. a 200 w resistor between the clock source and pin 16 will slow down the rise and fall times of the clock to reduce charge coupling of the clock. this will result in less clock feedthrough noise on the output signal. block diagra w + + inv a inv b clk v v + v + 1 3 8 14 hpa/na bpa lpa sa hpb/nb bpb lpb sb agnd 15k 15k 1067 bd + + 15 9 16 10 13 11 12 7 4 65
9 ltc1067/ltc1067-50 odes of operatio u w mode 1 in mode 1, the ratio of the external clock frequency to the center frequency of each 2nd order section is internally fixed at the parts nominal ratio. figure 3 illustrates mode 1 providing 2nd order notch, lowpass and bandpass outputs. mode 1 can be used to make high order butter- worth lowpass filters; it can also be used to make low q notches and for cascading 2nd order bandpass functions tuned at the same center frequency. mode 1 is faster than mode 3. please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . linear technologys universal switched-capacitor filters are designed with a fixed internal, nominal f clk /f o ratio. the ltc1067 has a 100:1 f clk /f o ratio and the ltc1067-50 has a 50:1 f clk /f o ratio. filter designs often require the f clk /f o ratio of each section to be different from the nominal ratio and in most cases different from each other. ratios other than the nominal value are possible with external resistors. operating modes use external resistors, connected in different arrangements to realize different f clk /f o ratios. by choosing the proper mode, the f clk /f o ratio can be increased or decreased from the parts nominal ratio. the choice of operating mode also effects the transfer function at the hp/n pins. the lp and bp pins always give the lowpass and bandpass transfer functions respectively, regardless of the mode utilized. the hp/n pins have a different transfer function depending on the mode used. mode 1 yields a notch transfer function. mode 3 yields a highpass transfer function. mode 2 yields a highpass- notch transfer function (i.e., a highpass with a stopband notch). more complex transfer functions, such as low- pass-notch, allpass or complex zeros, are achieved by summing two or more of the lp, bp or hp/n outputs. this is illustrated in sections mode 2n and mode 3a. choosing the proper mode(s) for a particular application is not trivial and involves much more than just adjusting the f clk /f o ratio. listed here are six of the nearly twenty modes available. to make the design process simpler and quicker, linear technology has developed the filtercad tm for windows ? design software. filtercad is an easy-to- use, powerful and interactive filter design program. the designer can enter a few filter specifications and the program produces a full schematic. filtercad allows the designer to concentrate on the filters transfer function and not get bogged down in the details of the design. alternatively, those who have experience with the linear technology family of parts can control all of the details themselves. for a complete listing of all the operating modes, consult the appendices of the filtercad manual or the help files in filtercad. filtercad can be obtained free of charge on the linear technology web site (http:// www.linear-tech.com) or you can order the filtercad cd-rom by contacting linear technologys marketing department. filtercad is a trademark of linear technology corporation. windows is a registered trademark of microsoft corporation. mode 1b mode 1b is derived from mode 1. in mode 1b (figure 4) two additional resistors r5 and r6 are added to lower the amount of voltage fed back from the lowpass output into the input of the sa (or sb) switched-capacitor summer. this allows the filters clock-to-center frequency ratio to be adjusted beyond the parts nominal ratio. mode 1b maintains the speed advantages of mode 1 and should be considered an optimum mode for high q designs with f clk to f cutoff (or f center ) ratios greater than the parts nominal ratio. figure 3. mode 1, 2nd order filter providing notch, bandpass and lowpass outputs + s agnd note: ratio = 100 for ltc1067 = 50 for ltc1067-50 r1 n bp lp v in 1067 f03 + s r2 r3 c c f o = ; f n = f o q = ; h on = ? ; h obp = h olp = h on r2 r1 r3 r1 r3 r2 f clk ratio
10 ltc1067/ltc1067-50 odes of operatio u w the parallel combination of r5 and r6 should be kept below 5k. please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . mode 3 in mode 3, the ratio of the external clock frequency to the center frequency of each 2nd order section can be ad- justed above or below the parts nominal ratio. figure 5 illustrates mode 3, the classical state variable configura- tion, providing highpass, bandpass and lowpass 2nd order filter functions. mode 3 is slower than mode 1. mode 3 can be used to make high order all-pole bandpass, lowpass and highpass filters. please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . mode 2 mode 2 is a combination of mode 1 and mode 3, shown in figure 6. with mode 2, the clock-to-center frequency ratio, f clk /f o , is always less than the parts nominal ratio. the advantage of mode 2 is that it provides less sensitivity to resistor tolerances than does mode 3. mode 2 has a highpass-notch output where the notch frequency depends solely on the clock frequency and is therefore less than the center frequency, f o . please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . + s agnd r1 hp bp lp v in 1067 f05 + s r2 r3 c c r4 f o = f clk ratio h ohp = ? ; h obp = ? ; note: ratio = 100 for ltc1067 = 50 for ltc1067-50 r2 r1 r3 r1 r4 r1 h olp = ? r3 r2 ? r2 r4 r3 (ratio)(0.32)(r4) ( ) 1 1 ? r3 (ratio)(0.32)(r4) ( ) 1 1 ? ( ) ? r2 r4 ; q = 1.005 figure 5. mode 3, 2nd order section providing highpass, bandpass and lowpass outputs figure 6. mode 2, 2nd order filter providing highpass notch, bandpass and lowpass outputs + s agnd r1 n bp lp v in 1067 f04 + s r2 r3 c c r5 r6 f o = ; f n = f o q = ; h on = ? ; h obp = h olp = ? r2 r1 r3 r1 r3 r2 f clk ratio ? r6 (r6 + r5) r2 r1 r6 + r5 r6 ? r6 (r6 + r5) () note: ratio = 100 for ltc1067 = 50 for ltc1067-50 figure 4. mode 1b, 2nd order filter providing notch, bandpass and lowpass outputs + s agnd r1 hpn bp lp v in 1067 f06 + s r2 r3 c c r4 f o = ; f n = f clk ratio ? r2 r4 1 + f clk ratio q = 1.005 r3 r2 ( ) ? r2 r4 1 + h ohpn = ? (ac gain, f >> f o ); h ohpn = r2 r1 r2 r1 r2 r1 1 r2 r4 1 + ( ) (dc gain) h obp = r3 r1 ; h olp = note: ratio = 100 for ltc1067 = 50 for ltc1067-50 r3 (ratio)(0.32)(r4) ( ) 1 1 ? r3 (ratio)(0.32)(r4) ( ) 1 1 ? 1 r2 r4 1 + ( )
11 ltc1067/ltc1067-50 odes of operatio u w mode 3a this is an extension of mode 3 where the highpass and lowpass outputs are summed through two external resis- tors, r h and r l , to create a notch (see figure 7). mode 3a is more versatile than mode 2 because the notch fre- quency can be higher or lower than the center frequency of the 2nd order section. the external op amp of figure 7 is not always required. when cascading the sections of the ltc1067, the highpass and lowpass outputs can be summed directly into the inverting input of the next section. please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . figure 7. mode 3a, 2nd order filter providing a highpass notch or lowpass notch output mode 2n this mode extends the circuit topology of mode 3a to mode 2 (figure 8) where the highpass-notch and lowpass outputs are summed through two external resistors, r h and r l , to create a lowpass output with a notch higher in frequency than the notch in mode 2. this mode, shown in figure 8, is most useful in lowpass elliptic designs. when cascading the sections of the ltc1067, the highpass- notch and lowpass outputs can be summed directly into the inverting input of the next section. please refer to the operating limits paragraph under appli- cations information for a guide to the use of capacitor c c . figure 8. mode 2n, 2nd order filter providing a lowpass notch output + s agnd r1 hp bp lp v in 1067 f07 + s r2 r3 r4 c c + external op amp or input op amp of the ltc1067, sides a or b highpass or lowpass notch output r g r l r h r2 r1 ( ) r g r h () f o = ; f n = h ohpn (f = ) = ; h olpn (f = 0) = f clk ratio f clk ratio ? r h r l ? r2 r4 q = 1.005 r3 r2 ? r2 r4 ( ) r4 r1 ( ) r g r l () note: ratio = 100 for ltc1067 = 50 for ltc1067-50 r3 (ratio)(0.32)(r4) ( ) 1 1 ? + s agnd r1 hp bp lp v in 1067 f08 + s r2 r3 r4 c c + external op amp or input op amp of the ltc1067, sides a or b lowpass notch output r g r l r h f o = f n = h olpn (f = 0)= + f clk ratio f clk ratio ? r h r l 1 + r2 r1 r g r l r g r h () 1 r2 r4 1 + ( ) ( ) ? r2 r4 1 + q = 1.005 r3 r2 ( ) ? r2 r4 1 + note: ratio = 100 for ltc1067 = 50 for ltc1067-50 r3 (ratio)(0.32)(r4) ( ) 1 1 ?
12 ltc1067/ltc1067-50 applicatio n s i n for m atio n wu u u a switched-capacitor integrator generally exhibits a higher input offset than a discrete rc integrator. the larger offset is mainly due to the charge injection from the cmos switches into the integrated capacitor. the integrators op amp offset, typically a couple of millivolts, also adds to the overall offset value. figure 9 shows the input offsets from a single 2nd order section. table 2 lists the formula for the output offset voltage for various modes and output pins. + hp/n bp + lp v os2 v os3 1067 f09 v os1 inv s table 2. output dc offsets for a second order section mode v oshp/n v osbp v oslp 1v os1 [1 + (r2/r3) + (r2/r1)] C (v os3 )(r2/r3) v os3 v oshp/n C v os2 1b v os1 [1 + (r2/r3) + (r2/r1)] C (v os3 )(r2/r3) v os3 (v oshp/n C v os2 )[1 + (r5/r6)] 2v os1 [1 + (r2/r3) + (r2/r1) + (r2/r4) C (v os3 )v os3 v oshp/n C v os2 (r2/r3)](r4/r2 + r4) + (v os2 )(r2/r2 + r4) 3v os2 v os3 v os1 [1 + (r4/r1) + (r4/r2) + (r4/r3)] C (v os2 ) (r4/r2) C (v os3 )(r4/r3) limits defined by the typical performance characteristics graphs, passband gain variations of 2db or more should be expected. clock feedthrough clock feedthrough is defined as the rms value of the clock frequency and its harmonics that are present at the filters output pins. the clock feedthrough is tested with the filters input grounded and depends on pc board layout and on the value of the power supplies. with proper layout techniques, the typical values of clock feedthrough are listed under electrical characteristics. any parasitic switching transients during the rising and falling edges of the incoming clock are not part of the clock feedthrough specifications. switching transients have fre- quency contents much higher than the applied clock; their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. the clock feedthrough, can be greatly reduced by adding a simple rc lowpass network at the final filter output. this rc will completely eliminate any switching transients. wideband noise the wideband noise of the filter is the total rms value of the devices noise spectral density and is used to deter- mine the operating signal-to-noise ratio. most of its fre- quency contents lie within the filter passband and cannot be reduced with post filtering. for a notch filter the noise of the filter is centered at the notch frequency. the total wideband noise ( m v rms ) is nearly independent of the value of the clock. the clock feedthrough specifica- tions are not part of the wideband noise. for a specific filter design, the total noise depends on the q of each section and the cascade sequence. operating limits the maximum q vs frequency (f o ) graphs, under typical performance characteristics, define an upper limit of operating q for each ltc1067 (or ltc1067-50) 2nd order section. these graphs indicate the power supply, f o and q value conditions under which a filter implemented with an ltc1067 will remain stable when operated at tempera- tures of 70 c or less. for a 2nd order section, a bandpass gain error of 3db or less is arbitrarily defined as a condition for stability. when the passband gain error begins to exceed 1db, the use of capacitor c c will reduce the gain error (capacitor c c is connected from the lowpass node to the inverting node of a 2nd order section). please refer to figures 3 through 8. the value of c c can be best determined experimentally, and as a guide it should be about 5pf for each 1db of gain error and not to exceed 15pf. when operating the ltc1067 near the figure 9. block diagram of a 2nd order section showing the input offsets
13 ltc1067/ltc1067-50 aliasing aliasing is an inherent phenomenon of switched-capacitor filters and occurs when the frequency of the input signals that produce the strongest aliased components have a frequency, f in , such as (f sampling C f in ) that falls into the filters passband. for both the ltc1067 and the ltc1067-50, the sampling frequency is twice f clk . if the input signal spectrum is not band limited, aliasing may occur. output loading the op amps on the ltc1067/ltc1067-50 have a rail-to- rail output stage. the output loading issues can be divided into resistive loading effects and capacitive loading ef- fects. resistive loading effects the maximum output signal swing. this effect is shown in the typical performance curves. note that the load on the output must include both the feedback resistor and any external load resistor. for example, consider the following situation: the part is running on split power supplies, the section is configured in mode 3, the r4 resistor is 20k and an external 20k load is connected from the lp node to ground. the load on the lp output is 20k in parallel with 20k, or 10k. all testing on the ltc1067/ltc1067-50 is done with a 10k load. for the best results, the load resistance on all output pins should be at least 10k. capacitive loading reduces the stability of the op amps. the signal at the output of a switched-capacitor filter is composed of a series of very small steps. the op amp must respond to a step and fully settle before the next step. as the stability of the op amp is decreased, the output step response has increased ringing and a much longer settling time. this longer settling time drastically lowers the maxi- mum usable clock speed and introduces errors. if the capacitive loading is sufficiently high, the stability will be decreased to the point of oscillation at the output. the ltc1067/ltc1067-50 are sensitive to capacitive load- ing. capacitive loading should be kept below 20pf. good, tight layout techniques should be maintained at all times. these parts should not drive long traces and never drive a long coaxial cable. when probing the ltc1067 or applicatio n s i n for m atio n wu u u ltc1067-50, always use a 10 probe. never use a 1 probe. a standard 10 probe has a capacitance of 10pf to 15pf while a 1 probes capacitance can be as high as 150pf. the 1 probe will probably cause oscillation. what to do with an unused section if the ltc1067 or ltc1067-50 is used as a single 2nd order filter, the other 2nd order section is not used. do not leave this section unconnected. if the section is uncon- nected, inputs and outputs are left to float to undetermined levels and oscillation may occur. the unused section should be connected as shown in figure 10. output voltage swing on a single supply voltage the typical performance curves show the output voltage swing limitations. the curves show the output signal swing, in volts peak-to-peak, versus the output load resis- tance. the peak-to-peak swing is limited by the following three considerations: the op amps output swings closer to the negative supply than the positive supply, the agnd pin is biased at the midpoint of the supplies and all operating modes are inverting. the op amps in the ltc1067/ltc1067-50 swing closer to the negative supply rail than the positive supply rail. the positive output voltage swing for single supply operation is shown in figures 11 and 12. the negative output voltage swing is about 15mv for the ltc1067 and 10mv for the ltc1067-50. the negative output voltage swing is nearly independent of load resistance since the load in this case is connected to the v C supply rail. for single supply applications, the on-chip resistor divider sets the voltage at the agnd pin to the midpoint of the v + and v C potentials. the agnd voltage is the reference for all internal op amps. if the input to the filter is at the v C rail, + v + 1067 f10 inv hp bp lp figure 10. connections for an unused section
14 ltc1067/ltc1067-50 applicatio n s i n for m atio n wu u u many applications are more concerned with the negative output swing than the positive output swing. interfacing to an adc running on a single 5v supply with a 4.096 reference voltage is a standard example. the ltc1067 or ltc1067-50 will easily reach the 4.096v level for a full- scale reading. the issue is how close does the output go to ground. the further the output is from ground, the more codes that are essentially lost. the previous example demonstrated that the lowest output voltage would be about 250mv, although, as is shown below, 15mv is achievable. to achieve a lower negative output swing voltage, the agnd voltage must be adjusted down below the midpoint. the agnd voltage is determined by two equal, on-chip resistors. these resistors are typically 15k each. while the ratio of these two resistors is tightly matched, the absolute value of the resistors is not tightly controlled. adjusting the agnd voltage by simply adding an external resistor can be done, but caution must be exercised. in figure 13, a resistor is used to adjust the agnd voltage for use with a 5v powered adc with a full-scale input of 4.096v. the resistor value was chosen carefully to assure that a 4.096v input signal to the filter yields a full-scale reading from the adc and a 0v input signal gives the lowest possible value (15mv for the ltc1067 and 10mv for the ltc1067-50). the circuit works well over tempera- ture and part variations. for this application, the 5v supply must be above 4.75v. load resistance (k to v ) positive output voltage swing (v) 5.0 4.5 4.0 3.5 3.0 2.5 1067 f11 10 0 2 4 6 8 12 14 16 18 20 ltc1067-50 ltc1067 figure 11. ltc1067/ltc1067-50 positive output voltage swing vs load resistance, 5v supply the output of the first section is near the positive rail (operating modes invert the signal). the output of the first stage will saturate at about 250mv (typical for 5v supply) from positive supply. the output from the second stage will be 250mv from the negative supply rail (assuming inversion again) even though the op amps output is capable of swinging to within 15mv. the positive output voltage swing being less than the negative swing, coupled with the agnd potential set at the midpoint of the supplies and inverting of the signal, yields the following equation for peak-to-peak output swing: v p-p swing = (v + C v C ) C 2(v + C v positive swing ) load resistance (k to v ) positive output voltage swing (v) 3.3 3.0 2.7 2.4 2.1 1.8 1.5 1067 f12 10 0 2 4 6 8 12 14 16 18 20 ltc1067-50 v s = 3v ltc1067 v s = 3.3v figure 12. ltc1067/ltc1067-50 positive output voltage swing vs load resistance, 3.3v/3v supplies 0.1 m f 1067 f13 64.9k 1% ltc1067 ltc1067-50 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b 5v (4.75v min ) 1 m f figure 13. power and agnd connections for 5v adc with 4.096v full scale
15 ltc1067/ltc1067-50 applicatio n s i n for m atio n wu u u figure 14 illustrates how a resistor adjusts the agnd voltage for use with a 3v/3.3v powered adc with a full- scale input of 2.048v. as in the previous circuit, the resistor value was chosen carefully to assure that a 2.048v input signal to the filter yields a full-scale reading from the adc and a 0v input signal gives the lowest possible value. for this application, the power supply must be above 2.7v for an ltc1067-50 filter and above 3v for an ltc1067 filter. figure 14. power and agnd connections for 3v/3.3v adc with 2.048v full scale 0.1 m f 1067 f14 33.2k 1% ltc1067 ltc1067-50 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b 3v to 3.6v (ltc1067) 2.7v to 3.6v (ltc1067-50) 1 m f semi-custom filter program linear technology has in place a program to deliver fully integrated filters, custom designed for any specified appli- cation. these semi-custom filters are based on an existing universal filter product with integrated, on-chip resistors. the final filter is then tested to the exact parameters defined for the application. the final result is a fully integrated, accurately tested solution in a smaller pack- age. for the ltc1067 or ltc1067-50 parts, a semi- custom filter comes in the so-8 package and requires only a clock and a decoupling capacitor. for more details on the semi-custom filter program, contact linear technologys marketing department. demonstration board there is a demonstration board available for the ltc1067/ ltc1067-50. demonstration board 150a has the ltc1067 part installed and the board 150b has the ltc1067-50 installed. the schematic for the board is shown in figure 15 and the assembly drawing is shown in figure 16. to obtain a demonstration board, call your local representa- tive or linear technologys marketing department. the demonstration board has all integrated circuits, con- nectors and decoupling capacitors installed. the board is ready to be configured with the appropriate resistors and jumper connections. there are two sets of power supply connections. one is for the ltc1067/ltc1067-50 and the other is for the buffer- ing op amp on the board. having separate connections gives the board the most flexibility. the two sets of supplies can be connected together if a common supply is desired. when configuring the board for split supply operation, a jumper wire must be installed in the jpagnd position. this connects the agnd pin of the device to the ground plane of the board. the jpvneg jumper must be left open. the power supply is then connected to v + , v C and gnd turrets (all of the gnd turrets on the board are the same). for single supply operation, insert a wire in the jpvneg jumper and leave the jpagnd jumper open. this connects the v C pin to the boards ground plane. the jpagnd jumper must be left open so that the on-chip resistor network can set the agnd potential at the midpoint of the supply. connect the power supply to v + and any gnd turret. the v C turret can be left open or shorted to the adjacent gnd turret. if the buffering op amp is run on the same single voltage supply, the voa + turret and the v + turrets must be connected together and the voa C turret must be shorted to the adjacent gnd turret. the j1 bnc connector is the clock input. there is a 200 w series resistor connected between the connector and the clk pin of the part. this resistor, coupled with the clk pins input capacitance, slows down the rise and fall times of the clock signal and decreases high frequency coupling. the clock input is not terminated to 50 w or 75 w . an external terminator should be used. jumpers jp51 and jp61 are connected in parallel with r51 and r61 respectively. jumper jp51 connects the lpa pin of the part with the sa pin. this can be used for operating modes 1 or 2. alternatively, a 0 w resistor in the r51 position fulfills the same requirement. the jp61 jumper connects the sa pin of the part to the agnd pin.
16 ltc1067/ltc1067-50 applicatio n s i n for m atio n wu u u this would be used for operating mode 3. here, a 0 w resistor in the r61 position also works. jumpers jp52 and jp62 perform the same functions on the b side of the part. the buffering amplifier can be configured for inverting or noninverting operation. for inverting applications, con- nect jumper jp2 positions 1 and 2. additionally, connect jumper jp4 for split supply applications or jp8 for a single supply. for a noninverting application, connect jumper jp2 positions 2 and 3. several other jumpers should be connected as follows: jp1: install a jumper wire from position 1 to position 2, leave the other positions open. jp5: install a jumper wire if split supply, leave open if single supply. jp6: leave open. jp7: install a jumper wire. jp9: install a jumper wire if single supply, leave open if split supply. ltc1067 or ltc1067-50 r1 200 1% clock in c7 0.1 f c8 0.1 f c9 10 f 36v c11 10 f 36v tp3 tp5 tp6 tp7 tp11 1067 f15 voa + voa v out 1/2 lt1498 1/2 lt1498 c2, 0.1 f c1 10 f, 6.3v jpvneg r52 r51 r41 r31 r21 r11 jp1 v in tp4 tp9 tp1 d1 mbr0630t1 tp10 v + c3 10 f 16v 1 2 4 3 r l2 r b2 r h2 c13 c10 0.1 f r4 12 3 3 8 1 4 2 jp52 v + nc v + sa lpa bpa hpa/na inv a 16 15 14 13 12 11 10 9 clk agnd v sb lpb bpb hpb/nb inv b 1 2 3 4 5 6 7 8 jp62 connect this jumper for dual supplies connect this jumper for single supplies. the ltc1067 has on-chip resistors to generate 1/2 supply for agnd jpagnd jp4 jp8 r2 tp2 tp8 v r62 + c6, 0.1 f j1 + 5 7 6 + r3 c12 c5 c4 10 f 16v jp3 + + jp7 jp9 jp6 jp5 r42 r l1 r b1 r h1 r32 r22 jp51 jp61 r61 + d2 mbr0630t1 + jp2 figure 15. schematic for the ltc1067/ltc1067-50 demo board
17 ltc1067/ltc1067-50 frequency (khz) 12468 gain (db) 10 1067 ta05c 1.00 0.75 0.50 0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 20 c in1 = 1500pf ?5% c in1 = 1500pf + 5% c in1 = 1500pf applicatio n s i n for m atio n wu u u passband gain variation due to c in frequency response (f cutoff = 10khz) frequency (khz) 1 gain (db) 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 10 100 1067 ta05b 1067 ta05a ltc1067 v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b 5v v in r in1 16.9k c in1 1500pf 5% r in2 22.6k r32, 29.4k r42, 47.5k r22, 45.3k r41, 20k r31, 47.5k r21, 22.6k r h1 , 118k r l1 , 24.3k v out f clk ?v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 0.1 m f 0.1 m f v s 5v 5v 3v f cutoff 20k 15k 10k 5k c in1 750pf 1000pf 1500pf 3000pf f clk 2mhz 1.5mhz 1mhz 500khz typical applicatio n s u 5th order lowpass with input rc (fixed frequency) figure 16. silkscreen for the ltc1067/ltc1067-50 demo board
18 ltc1067/ltc1067-50 typical applicatio n s u 1khz linear phase bandpass filter ltc1067 v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b r32, 53.6k r42, 80.6k r22, 10k r61 40.2k r51 4.99k r31, 56.2k r21, 10k r11 60.4k r b1 , 36.5k v out 100khz ?v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 0.1 m f 0.1 m f 5v v in 1067 ta06a v s 5v 5v (or 2.5v) 3v (or 1.5v) maximum frequency 5khz 2.5khz 2.2khz center gain and group delay vs frequency frequency (hz) 10 5 0 ? ?0 ?5 ?0 ?5 ?0 ?5 ?0 3.0 2.5 2.0 1.5 1.0 0.5 0 gain (db) delay (ms) 1067 ta06b 600 760 920 1080 1240 1400 gain delay input (500mv/div) output (50mv/div) 1067 ta06c 5ms/div sine burst response single supply, 4th order bandpass filter f center = f clk /64, C 3db bw = f center /20 ltc1067-50 v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b r32, 255k r62 8.66k r52 4.99k r22, 4.99k r61 7.32k r51 4.99k r31, 255k r21, 4.99k r b1 , 115k v out 64khz 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 m f 0.1 m f 1067 ta07a v s maximum f center single 5v 12khz single 3.3v 7.5khz single 3v 5.5khz noise v s (filter input at v + /2) single 5v 426 v rms single 3.3v 333 v rms single 3v 290 v rms r11 267k 5v v in
19 ltc1067/ltc1067-50 typical applicatio n s u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. frequency (khz) 1 0 ? ? ? ? ? ? ? ? ? gain (db) 1067 ta07b 960 980 1000 1020 1040 gain vs frequency v in (500mv/div) v out (50mv/div) 1067 ta07d 5ms/div sine burst response gain vs frequency frequency (khz) ? 0 5 10 15 20 25 30 35 40 45 gain (db) 1067 ta07b 500 700 900 1100 1300 1500 single supply, 4th order bandpass filter v s = 5v, f clk = 64khz ltc1067 v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb bpb hpb/nb inv b r32, 75k r42, 5.23k r22, 4.99k r61 15k r51 4.99k r31, 232k r21, 4.99k r11 232k r12,140k v out2 v out1 v in2 v in1 150khz 5v ?v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 0.1 m f 0.1 m f 1067 ta08a ltc1067 dual bandpass filters v s = 5v, f clk = 150khz (f center1 =1.3khz, f center2 = 2.1khz) frequency response frequency (khz) 5 0 ? ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 gain (db) 1067 ta08b 12345 v out1 v out2 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 1197 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.025 (0.635) bsc 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9
20 ltc1067/ltc1067-50 ? linear technology corporation 1997 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. 10675fs, sn1067 lt/tp 0698 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com part number description comments ltc1068-25 high speed quad universal building block filter 25:1 clock-to-f o ratio ltc1068-50 low power quad universal building block filter 50:1 clock-to-f o ratio ltc1068-200 low noise, oversampled quad universal building block filter 200:1 clock-to-f o ratio ltc1068 quad universal building block filter 100:1 clock-to-f o ratio ltc1562 quad, universal, continuous time building block 10khz < f c < 150khz related parts typical applicatio n u 1.02khz notch filter for telecom system 0.1 m f 1067 ta03 ltc1067 5v r52, 4.99k* r32, 464k r22, 75k r31, 61.9k r51, 4.99k* r61, 9.88k* r21, 10k r11, 18.7k v in *** 1 m f f clk = 125khz 1 2 3 4 5 6 7 8 16 15 14 13 12 200 r62, 10k* rh1, 40.2k c21, 300pf** c22, 30pf** v out r51, r61, r52, r62 are 0.1% tolerance resistors c21 and c22 improve the notch depth where * ** *** 1 2 p (r2x)(c2x) (30)(f notch ) < < (75)(f notch ) without c21 and c22 the notch depth is limited to ?5db v in 1.25v p-p v + nc v + sa lpa bpa hpa/na inv a clk agnd v sb lpb 11 10 9 hpb/nb inv b bpb frequency response frequency (khz) 800 gain (db) 900 1000 1100 1067 ta04 1200 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 s16 0695 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610)

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